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Author	SHA1	Message	Date
XMRig	6adba6dad4	Removed unnecessary check.	2019-12-15 12:02:45 +07:00
XMRig	b346507975	Added enable_1gb_pages.sh	2019-12-15 03:13:52 +07:00
XMRig	fb5b873524	Added missing tag.	2019-12-15 01:52:20 +07:00
XMRig	a6f381403c	Added WinRing0 driver binary.	2019-12-15 01:48:48 +07:00
XMRig	5d0fd2dc8e	Unified Linux/Windows MSR log messages.	2019-12-15 01:32:41 +07:00
xmrig	1ad6b5504c	Merge pull request #1416 from SChernykh/dev ... Fixed thread count for MSR mod	2019-12-14 22:41:00 +07:00
SChernykh	222fcfae87	Fixed thread count for MSR mod	2019-12-14 16:30:46 +01:00
XMRig	5a2c3d8396	v5.3.0-dev	2019-12-14 22:30:41 +07:00
XMRig	687617de25	Merge branch 'master' into dev	2019-12-14 22:29:57 +07:00
xmrig	a682ae3299	Merge pull request #1414 from SChernykh/dev ... MSR mod for Windows	2019-12-14 22:12:08 +07:00
SChernykh	2e6523aa10	MSR mod for Windows	2019-12-14 16:04:37 +01:00
XMRig	29591609f5	v5.2.1	2019-12-14 13:15:19 +07:00
XMRig	b15da20f9c	Merge branch 'dev'	2019-12-14 13:14:09 +07:00
xmrig	8f2f3d73df	Update CHANGELOG.md	2019-12-14 02:27:19 +07:00
XMRig	7d7459100b	Removed extra space.	2019-12-13 00:38:07 +07:00
xmrig	8a0c8d9709	Merge pull request #1408 from SChernykh/dev ... RandomX boost script for Linux	2019-12-13 00:32:03 +07:00
SChernykh	8592561b7a	RandomX boost script for Linux	2019-12-12 18:25:28 +01:00
XMRig	7ff465053b	Added additional MSR registers for Ryzen CPUs.	2019-12-12 14:21:15 +07:00
XMRig	c62ac89081	Fixed potential division by 0.	2019-12-12 14:09:18 +07:00
XMRig	1c58e28124	Don't build Rx_linux.cpp on ARM.	2019-12-11 21:20:37 +07:00
XMRig	96ee721d21	Fixed MSR.	2019-12-11 20:09:25 +07:00
XMRig	de7ed2b968	Added support for AMD specific MSR registers.	2019-12-11 19:37:13 +07:00
XMRig	4fb3086c1c	Fixed --randomx-wrmsr option without parameters.	2019-12-11 19:16:01 +07:00
XMRig	5ab17fcd46	v5.2.1	2019-12-11 17:58:44 +07:00
XMRig	ff1849b63b	Merge branch 'master' into dev	2019-12-11 17:58:03 +07:00
xmrig	9db3fb280e	Update CHANGELOG.md	2019-12-11 16:22:05 +07:00
XMRig	06e105821a	v5.2.0	2019-12-11 14:06:53 +07:00
XMRig	a0046e325c	Merge branch 'dev'	2019-12-11 14:06:21 +07:00
xmrig	e84bad4eca	Update CHANGELOG.md	2019-12-11 13:41:48 +07:00
XMRig	fc5b339f04	Added new screenshot.	2019-12-11 13:15:31 +07:00
XMRig	96cfdda9a1	Added RandomX option "wrmsr" with command line equivalent --randomx-wrmsr=N.	2019-12-10 23:57:29 +07:00
XMRig	3b4b230cab	Added CPU vendor enum.	2019-12-10 12:49:42 +07:00
XMRig	6163d27f14	Added command line option --randomx-1gb-pages	2019-12-10 11:56:31 +07:00
xmrig	f3f75fb788	Update CHANGELOG.md	2019-12-10 11:19:11 +07:00
xmrig	d07a806123	Merge pull request #1401 from SChernykh/dev ... More optimizations for Ryzen	2019-12-10 09:55:52 +07:00
SChernykh	ef522f6404	Update jit_compiler_x86_static.S	2019-12-09 20:30:37 +01:00
SChernykh	763691fa4b	More optimizations for Ryzen	2019-12-09 20:29:05 +01:00
xmrig	2491149d61	Merge pull request #1400 from SChernykh/dev ... Fixed assembly selection for RandomX when it's on Auto	2019-12-10 01:01:12 +07:00
SChernykh	9bc13813ba	Fixed assembly selection for RandomX when it's on Auto	2019-12-09 18:59:49 +01:00
XMRig	3edaebb4cf	Move "1gb-pages" option to "randomx" object.	2019-12-09 21:42:40 +07:00
XMRig	558c524e2a	Added missing Cpu::release call.	2019-12-09 01:07:42 +07:00
XMRig	d6582de09b	v5.2.0-dev	2019-12-08 23:23:03 +07:00
XMRig	d32df84ca5	Memory allocation refactoring.	2019-12-08 23:17:39 +07:00
xmrig	8a13e0febd	Merge pull request #1397 from SChernykh/dev ... Fix GCC compilation	2019-12-08 22:52:18 +07:00
SChernykh	028b335bac	Fix GCC compilation	2019-12-08 16:51:37 +01:00
xmrig	d7d09159c1	Merge pull request #1396 from SChernykh/dev ... Optimized dataset read for Ryzen CPUs	2019-12-08 22:24:26 +07:00
SChernykh	ffec421408	Fixed indentation	2019-12-08 16:20:46 +01:00
SChernykh	d0df824599	Optimized dataset read for Ryzen CPUs ... Removed register dependency in dataset read, +0.8% speedup on average.	2019-12-08 16:14:02 +01:00
XMRig	4dec063472	Fix summary.	2019-12-08 14:30:44 +07:00
XMRig	86e25a13e3	New summary information about 1GB pages.	2019-12-08 14:21:28 +07:00