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037abd7037
This is a workaround for total L2 cache size calculation of Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue. These processors have L2 cache shared by 2 cores. There is maybe more CPU with L2 shared cache, but I am sure that these models are concerned and they are not so numerous. A better way would be to modify libcpuid to implement L2 cache counting.
124 lines
3.6 KiB
C++
124 lines
3.6 KiB
C++
/* XMRig
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* Copyright 2010 Jeff Garzik <jgarzik@pobox.com>
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* Copyright 2012-2014 pooler <pooler@litecoinpool.org>
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* Copyright 2014 Lucas Jones <https://github.com/lucasjones>
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* Copyright 2014-2016 Wolf9466 <https://github.com/OhGodAPet>
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* Copyright 2016 Jay D Dee <jayddee246@gmail.com>
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* Copyright 2016-2017 XMRig <support@xmrig.com>
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libcpuid.h>
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#include <math.h>
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#include <string.h>
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#include "Cpu.h"
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bool Cpu::m_l2_exclusive = false;
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char Cpu::m_brand[64] = { 0 };
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int Cpu::m_flags = 0;
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int Cpu::m_l2_cache = 0;
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int Cpu::m_l3_cache = 0;
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int Cpu::m_sockets = 1;
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int Cpu::m_totalCores = 0;
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int Cpu::m_totalThreads = 0;
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int Cpu::optimalThreadsCount(int algo, bool doubleHash, int maxCpuUsage)
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{
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if (m_totalThreads == 1) {
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return 1;
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}
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int cache = 0;
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if (m_l3_cache) {
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cache = m_l2_exclusive ? (m_l2_cache + m_l3_cache) : m_l3_cache;
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}
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else {
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cache = m_l2_cache;
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}
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int count = 0;
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const int size = (algo ? 1024 : 2048) * (doubleHash ? 2 : 1);
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if (cache) {
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count = cache / size;
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}
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else {
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count = m_totalThreads / 2;
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}
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if (count > m_totalThreads) {
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count = m_totalThreads;
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}
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if (((float) count / m_totalThreads * 100) > maxCpuUsage) {
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count = (int) ceil((float) m_totalThreads * (maxCpuUsage / 100.0));
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}
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return count < 1 ? 1 : count;
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}
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void Cpu::initCommon()
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{
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struct cpu_raw_data_t raw = { 0 };
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struct cpu_id_t data = { 0 };
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cpuid_get_raw_data(&raw);
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cpu_identify(&raw, &data);
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strncpy(m_brand, data.brand_str, sizeof(m_brand) - 1);
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m_totalThreads = data.total_logical_cpus;
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m_sockets = m_totalThreads / data.num_logical_cpus;
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if (m_sockets == 0) {
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m_sockets = 1;
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}
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m_totalCores = data.num_cores * m_sockets;
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m_l3_cache = data.l3_cache > 0 ? data.l3_cache * m_sockets : 0;
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// Workaround for AMD CPUs https://github.com/anrieff/libcpuid/issues/97
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if (data.vendor == VENDOR_AMD && data.ext_family >= 0x15 && data.ext_family < 0x17) {
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m_l2_cache = data.l2_cache * (m_totalCores / 2) * m_sockets;
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m_l2_exclusive = true;
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}
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// Workaround for Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue
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// These processors have L2 cache shared by 2 cores.
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else if (data.vendor == VENDOR_INTEL && data.family == 0x06 && (data.model == 0x0E || data.model == 0x0F || data.model == 0x07)) {
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int l2_count_per_socket = m_totalCores > 1 ? m_totalCores / 2 : 1;
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m_l2_cache = data.l2_cache > 0 ? data.l2_cache * l2_count_per_socket * m_sockets : 0;
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}
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else{
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m_l2_cache = data.l2_cache > 0 ? data.l2_cache * m_totalCores * m_sockets : 0;
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}
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# if defined(__x86_64__) || defined(_M_AMD64)
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m_flags |= X86_64;
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# endif
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if (data.flags[CPU_FEATURE_AES]) {
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m_flags |= AES;
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}
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if (data.flags[CPU_FEATURE_BMI2]) {
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m_flags |= BMI2;
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}
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}
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