Ecosystem/xmrig
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Author SHA1 Message Date
XMRig
aec31c43c0 Better v1 PoW implementation, added variant option. 2018-03-12 22:29:44 +07:00
XMRig
83e5832bc1 Some small fixes. 2018-03-12 14:44:23 +07:00
XMRig
244ca93aa4 Change donation address to separate old and new versions. 2018-03-09 13:15:55 +07:00
XMRig
ff68c047f9 v2.5.0-dev 2018-03-09 01:49:24 +07:00
XMRig
b662cb77a4 Revert changes in Api class, single threaded http server will not be included in 2.5 release. 2018-03-09 01:47:44 +07:00
XMRig
3e2863dca5 Merge branch 'vtnerd-monero-v1-pow' into dev 
# Conflicts:
#	src/api/Httpd.cpp
#	src/api/Httpd.h
 2018-03-09 01:41:47 +07:00
xmrig
6e95b0d052
Update CHANGELOG.md 2018-03-09 01:30:32 +07:00
xmrig
da4aa69c89
Update CHANGELOG.md 2018-03-09 00:56:29 +07:00
XMRig
84970e9e9b Added coin field support added in xmrig-proxy 2.5. 2018-03-09 00:50:06 +07:00
XMRig
37ac1aa62c Automatically enable nicehash when use with upcoming xmrig-proxy 2.5. 2018-03-07 21:56:43 +07:00
XMRig
69b8a4faf1 Added option to disable Monero v7 PoW, may useful in future if other coins update their network to v7 without PoW change. 2018-03-07 19:12:18 +07:00
XMRig
8a6988d381 Added full IPv6 support. 2018-03-07 16:38:58 +07:00
XMRig
79779b51da Added reference hashes. 2018-03-07 15:32:44 +07:00
XMRig
8b60585004 PoW changes WIP 2018-03-06 21:34:20 +07:00
XMRig
df6a397e52 Update copyright and move version into Job class. 2018-03-06 17:06:07 +07:00
XMRig
274c6306a8 Merge branch 'monero-v1-pow' of https://github.com/vtnerd/xmrig into vtnerd-monero-v1-pow 2018-03-06 16:37:33 +07:00
XMRig
a398c8af2f Fixed regression (all versions since 2.4 affected) fragmented responses from pool/proxy parsed incorrectly. 2018-03-05 13:54:21 +07:00
XMRig
fc82cf1cf2 #428 Fixed regression with CPU cache size detection. 2018-03-05 02:15:05 +07:00
Lee Clagett
48b1de0b59 Changes for the Monero v1 PoW 2018-03-02 22:17:29 +00:00
XMRig
3edc30d067 Use adaptive timer instead of idle handler for HTTP server. 2018-03-01 09:53:27 +07:00
XMRig
ff6dc727f5 Added XMRIG_DEPS cmake variable for unified dependencies. 2018-02-21 00:52:52 +07:00
XMRig
a0d4e4ed3f Run internal http server in main loop to avoid requirement to thread synchronization. 2018-02-20 23:22:34 +07:00
XMRig
71759e3752 Merge branch 'master' into dev 2018-02-20 22:48:39 +07:00
xmrig
79345119c6
Update CHANGELOG.md 2018-02-19 15:58:44 +07:00
XMRig
9af8ceb063 v2.4.5 RC 2018-02-19 04:31:50 +07:00
xmrig
f5a0429f0d
Update README.md 2018-02-19 04:17:50 +07:00
xmrig
cc22c9d61c
Update README.md 2018-02-18 05:49:37 +07:00
xmrig
45f5afd2b7
Merge pull request #379 from DeadManWalkingTO/master 
Update README.md
 2018-02-18 05:48:09 +07:00
xmrig
c9acc2912e
Update CHANGELOG.md 2018-02-18 05:32:36 +07:00
xmrig
f0604d1e97
Update README.md 2018-02-18 05:06:10 +07:00
XMRig
531c657b64 Merge branch 'master' of github.com:xmrig/xmrig 2018-02-08 17:35:20 +07:00
XMRig
c50ccd4e06 Merge branch 'Foudge-master' 2018-02-08 17:34:33 +07:00
XMRig
184f79ad3f Fix code style, replace tabs to space #2. 2018-02-08 17:21:12 +07:00
XMRig
e78e810cfe Fix code style, replace tabs to space. 2018-02-08 17:02:32 +07:00
XMRig
c804ef1888 Merge branch 'master' of https://github.com/Foudge/xmrig into Foudge-master 2018-02-08 16:56:20 +07:00
Foudge
037abd7037 Correct L2 cache size calculation for Intel Core 2 family 
This is a workaround for total L2 cache size calculation of Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue. These processors have L2 cache shared by 2 cores.

There is maybe more CPU with L2 shared cache, but I am sure that these models are concerned and they are not so numerous.
A better way would be to modify libcpuid to implement L2 cache counting.
 2018-02-03 16:31:13 +01:00
DeadManWalking
75f462f0e1
Update README.md 2018-02-02 00:58:11 +02:00
DeadManWalking
9f92449e15
Update README.md 2018-02-02 00:54:58 +02:00
DeadManWalking
a917590862
Update README.md 2018-02-02 00:14:39 +02:00
DeadManWalking
41b92740ea
Merge pull request #1 from xmrig/master 
!
 2018-02-01 23:02:32 +02:00
Foudge
d2964576c7 Compilation error under FreeBSD 
ULONG is not recognized under this OS, so replaced it with more portable definition.
 2018-01-28 18:13:00 +01:00
Foudge
9a28ad590c up to 20% perf increase with Cryptonight with non-AES CPU 
This time, the performance increase is got with MSVC and GCC. On non-AES CPU, there were an useless load/store SSE2 register. The last MSVC "hack" is replaced by a portable code and he's more complete (a load is saved).

On my C2Q6600, with 3 thread, I have +16% with MSVC2015 and +20% with GCC 7.3, compared to official 2.4.4 version.
 2018-01-28 12:58:19 +01:00
Foudge
15fe6ce23f Remove compilation warnings under MSVC 2018-01-27 11:42:22 +01:00
xmrig
17f90de677
Merge pull request #353 from Foudge/master 
up to 15% boost on CryptoNight algo with non-AES CPU
 2018-01-26 00:53:22 +07:00
XMRig
631fd755c8 #341 Added option --dry-run. 2018-01-20 20:43:31 +07:00
Foudge
9bceb65ad8 +15% boost with non-AES CPU 
Performance boost validated on Core 2 Quad processor under Windows 10.
But it's Windows/MS Visual C++ specific.
 2018-01-20 10:43:56 +01:00
XMRig
56ffa7af79 #341 Fix wrong exit code. 2018-01-20 12:58:43 +07:00
xmrig
f210708f3b
Merge pull request #324 from stanz2g/master 
can build without microhttpd when WITH_HTTPD=OFF
 2018-01-20 01:35:12 +07:00
xmrig
916cf0ae0d
Update CHANGELOG.md 2018-01-11 15:08:24 +07:00
XMRig
e6540229cb #328 Added guard to prevent paused message spam and crash. 2018-01-10 22:55:45 +07:00