Commit graph

59 commits

Author SHA1 Message Date
XMRig
4263c6c381 Added hwloc version display. 2019-07-23 07:45:00 +07:00
XMRig
b27fc6fd5d hwloc used for CPU information. 2019-07-23 07:12:56 +07:00
XMRig
b02e596853 Strip extra spaces from CPU brand string and improved BasicCpuInfo. 2019-07-23 00:40:24 +07:00
XMRig
6f93b7b38d Removed unused code. 2019-07-17 15:28:59 +07:00
XMRig
2bf5ffb2df Class Mem replaced to VirtualMemory. 2019-07-17 04:57:58 +07:00
XMRig
62edb2fc0a Move CPU information classes to new location. 2019-06-29 09:51:23 +07:00
XMRig
dd875c7c37 Added class CpuConfig. 2019-06-28 22:28:40 +07:00
XMRig
66d62de681 Merge Assembly enum and Asm class. 2019-06-28 13:08:08 +07:00
XMRig
1f0e3e501c Implemented new style algorithm definitions (except ARM), removed Algo and Variant enums. 2019-06-13 22:08:52 +07:00
XMRig
d7f42d54ad Added initial support for per pool algo option (mining code is broken). 2019-06-10 20:46:29 +07:00
XMRig
d587eebaf2 Move files. 2019-06-04 19:20:33 +07:00
XMRig
e39ddeeea2 Removed IConfigCreator/ConfigCreator and changed file structure. 2019-03-30 21:27:54 +07:00
XMRig
01ad6bf2d9 Added new HTTP server (tiny wrapper on top of libuv + http_parser), removed libmicrohttpd support. 2019-03-29 12:33:11 +07:00
XMRig
725796a1ab New API settings. 2019-03-29 02:31:56 +07:00
XMRig
3f4886bb86 Fix CPU info colors. 2019-03-27 19:29:29 +07:00
XMRig
ba910a46ba Fix accidentally removed code. 2019-03-27 15:56:31 +07:00
XMRig
f43929db98 New log support. 2019-03-27 01:29:37 +07:00
XMRig
ced25c3fa0 Log subsystem rewritten, to handle both color and not color logs simultaneously and overall simplicity. 2019-03-26 19:56:35 +07:00
XMRig
0907d1eb0c Added "donate-over-proxy" option. 2019-03-19 00:16:30 +07:00
XMRig
ba68fb6c53 Added real graceful exit. 2019-03-16 00:44:15 +07:00
XMRig
ba01f2a9c4 Rename files. 2019-03-15 01:50:35 +07:00
XMRig
dbdcc14672 Move Pool.h/Pool.cpp. 2019-02-16 09:56:08 +07:00
XMRig
bd4bc9ba4d Added reference implementation for cn/gpu (cn-gpu). 2019-02-03 14:44:23 +07:00
XMRig
06a84499d7 Fixed MSYS2 build & copyright 2018-10-22 23:08:29 +07:00
SChernykh
4b91978af6 Added asm optimized code for AMD Bulldozer 2018-10-21 18:29:03 +02:00
XMRig
c2fcf23855 Implemented "asm" option. 2018-09-24 14:19:26 +03:00
XMRig
ee4d980955 Old static class Cpu replaced to interface ICpuInfo. 2018-09-23 17:51:56 +03:00
XMRig
bc9130ded3 Show TLS version. 2018-09-16 06:35:49 +03:00
XMRig
2f3939396e Move shared summary to xmrig::CommonConfig. 2018-09-16 05:04:20 +03:00
XMRig
812cd9760f Added debug thread log. 2018-09-15 16:48:57 +03:00
XMRig
009bd1a507 Sync changes with amd miner and update summary. 2018-06-01 01:48:31 +07:00
XMRig
ca149d2eed Sync changes with proxy. 2018-04-25 14:48:32 +07:00
XMRig
b9fec2fcc4 Added support for "rig id" protocol extension. 2018-04-23 13:20:43 +07:00
XMRig
36a612af9a Move logging code to common folder. 2018-04-20 18:54:58 +07:00
XMRig
2d22f2aeff Move shared network code to common folder. 2018-04-20 13:44:30 +07:00
XMRig
ad94e9a7d2 Simplify ARM implementation. 2018-04-19 11:54:11 +07:00
XMRig
9125b6c251 Rewrite memory allocation. 2018-04-15 11:08:47 +07:00
XMRig
a73ad9b089 Fixed build with APP_DEBUG. 2018-04-11 08:29:02 +07:00
XMRig
36ef254c73 Rename class Url to Pool. 2018-04-11 06:09:34 +07:00
XMRig
77207eaaae Fix build with APP_DEBUG. 2018-04-09 20:38:02 +07:00
XMRig
a042cbf885 Added classes IThread, CpuThread and API endpoint "GET /1/threads". 2018-04-01 22:49:21 +07:00
XMRig
af0a6fdf20 Small fixes. 2018-03-31 17:51:33 +07:00
XMRig
aac7b0404a Options class replaced to xmrig::Config. 2018-03-31 16:29:47 +07:00
XMRig
4b00eb4a9f #196 Fix Linux build. 2017-11-17 12:59:46 +03:00
XMRig
d0db4770ed Added API port to summary. 2017-09-02 15:50:27 +03:00
XMRig
0b5587fd6a Add commands help. 2017-07-23 10:04:23 +03:00
XMRig
ebf54c6d04 Fix warnings on Linux. 2017-07-18 22:38:38 +03:00
XMRig
970b5d1964 Add FailoverStrategy. 2017-07-01 20:53:42 +03:00
XMRig
c0dcfc2a97 Initial multiple pools support [2/2]. 2017-06-27 06:32:17 +03:00
XMRig
952017ae7a Initial multiple pools support [1/2]. 2017-06-26 21:13:05 +03:00