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Author	SHA1	Message	Date
XMRig	ad9ae6a143	Merge branch 'dev' of github.com:xmrig/xmrig into dev	2019-12-29 15:36:39 +07:00
XMRig	a5b0bc04cc	Add "cn/ultra" alias for tlo-pool.raasu.org pool.	2019-12-29 15:36:05 +07:00
xmrig	f491e99bf9	Update CHANGELOG.md	2019-12-29 03:43:10 +07:00
XMRig	402c44b547	Added "cn-pico/tlo".	2019-12-29 00:29:19 +07:00
XMRig	ac4086b273	Fix build.	2019-12-28 02:00:08 +07:00
XMRig	f00769f758	Code style cleanup.	2019-12-28 01:45:54 +07:00
xmrig	6ceb4dfc4f	Merge pull request #1465 from SChernykh/dev ... Fix for 1st-gen Ryzen crashes	2019-12-27 18:26:26 +07:00
SChernykh	3a2941b719	Fix for 1st-gen Ryzen crashes	2019-12-27 12:40:38 +02:00
xmrig	99826a6b51	Update CHANGELOG.md	2019-12-27 15:03:24 +07:00
XMRig	4a9a7434f6	Revert Platform::setProcessPriority	2019-12-27 03:19:03 +07:00
XMRig	dbb721cb5e	Removed "rx/v" algorithm.	2019-12-26 22:34:19 +07:00
xmrig	2a93bb2cee	Update CHANGELOG.md	2019-12-25 05:01:19 +07:00
XMRig	7dfb4d9dc0	v5.5.0-dev	2019-12-25 04:53:38 +07:00
XMRig	22eca8e0d5	Fixed memory allocation checks.	2019-12-25 04:39:21 +07:00
XMRig	ecb46643e2	Added support for alternative CUDA plugin API.	2019-12-25 00:35:43 +07:00
xmrig	73d959a259	Update ALGORITHMS.md	2019-12-24 03:48:39 +07:00
XMRig	a95b179a60	Merge branch 'dev' of github.com:xmrig/xmrig into dev	2019-12-24 02:05:00 +07:00
XMRig	2e4a83547d	Add console title for Windows.	2019-12-24 02:04:34 +07:00
xmrig	fd30294ca0	Merge pull request #1461 from suanlian1/patch-1 ... Monero already changed PoW on Nov 30, 2019	2019-12-24 01:07:44 +07:00
sairog	9b16a2736a	Update README.md ... Monero already changed PoW on Nov 30, 2019. Also minor text corrections.	2019-12-23 23:23:16 +05:30
XMRig	ea7aa4ccef	Fixed MSVC build.	2019-12-23 00:37:43 +07:00
XMRig	d81845e1ab	Merge branch 'feature-env' into dev	2019-12-23 00:29:38 +07:00
XMRig	f9d07229b4	Add extra variables.	2019-12-23 00:28:57 +07:00
XMRig	2d15c10e0f	Added ENV support for "loader" option.	2019-12-22 19:48:33 +07:00
XMRig	5bd6a1c028	Added ENV support for "user", "pass" and "rig-id" fields.	2019-12-22 19:09:30 +07:00
XMRig	356e666e61	Added Env class.	2019-12-22 18:09:26 +07:00
XMRig	bdf12bca0f	Make Process::location static.	2019-12-22 13:26:06 +07:00
XMRig	c44ae06d54	Added --randomx-no-rdmsr command line option.	2019-12-21 23:57:25 +07:00
XMRig	c7de9e6561	v5.4.1-dev	2019-12-21 23:42:18 +07:00
XMRig	00c9f89213	Merge branch 'master' into dev	2019-12-21 23:41:44 +07:00
XMRig	8f2a92c3ec	v5.4.0	2019-12-21 16:12:02 +07:00
XMRig	69e67784d3	Merge branch 'dev'	2019-12-21 16:11:25 +07:00
xmrig	cd7f73a31c	Update ALGORITHMS.md	2019-12-21 13:40:42 +07:00
XMRig	98cfe7ed37	Added extra error message.	2019-12-20 23:44:32 +07:00
XMRig	449617d717	Allow use old CUDA plugin.	2019-12-20 21:10:13 +07:00
xmrig	a25042db72	Update CHANGELOG.md	2019-12-20 04:16:28 +07:00
XMRig	049caabdae	Add missing algorithm name alias.	2019-12-20 04:08:47 +07:00
XMRig	81b1cccb0b	Merge branch 'Spudz76-dev-rxv' into dev	2019-12-20 04:06:25 +07:00
XMRig	2911bb3a81	Fix OpenCL.	2019-12-20 04:05:09 +07:00
Tony Butler	45412a2ace	Add MoneroV (rx/v) algorithm [based on MoneroOcean/master]	2019-12-18 16:17:22 -07:00
XMRig	f4cedd7b63	Fixed MsrItem serialization.	2019-12-19 03:49:32 +07:00
XMRig	3e3d34b3ce	Allow number value for "wrmsr" option only for Intel.	2019-12-19 03:28:05 +07:00
XMRig	12fb27e2cf	Use MsrItem::kNoMask.	2019-12-19 03:20:48 +07:00
xmrig	a1e8c1353f	Merge pull request #1443 from SChernykh/dev ... Fixed crash with GCC compiler	2019-12-18 23:45:36 +07:00
SChernykh	c01c035269	Fixed crash with GCC compiler	2019-12-18 17:32:57 +01:00
xmrig	eeb8bbe5bc	Merge pull request #1439 from SChernykh/dev ... Add vzeroupper for processors with AVX	2019-12-18 18:32:17 +07:00
SChernykh	f85aba5d21	Fixed AVX detection	2019-12-18 12:20:21 +01:00
SChernykh	f8bf8fddd9	Update jit_compiler_x86_static.S	2019-12-18 09:13:21 +01:00
SChernykh	7459677fd5	Add vzeroupper for processors with AVX ... To avoid false dependencies on upper 128 bits of YMM registers.	2019-12-18 09:12:25 +01:00
xmrig	c0b0628d59	Merge pull request #1438 from SChernykh/dev ... Added bit masks for MSR registers	2019-12-18 11:44:06 +07:00