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Merge pull request #3346 from SChernykh/dev
ARM64 JIT: don't use `x18` register
This commit is contained in:
xmrig
GitHub
commit
fee51b20fa
2 changed files with 75 additions and 77 deletions
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@ -131,8 +131,8 @@ void JitCompilerA64::generateProgram(Program& program, ProgramConfiguration& con
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// and w16, w10, ScratchpadL3Mask64
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emit32(0x121A0000 | 16 | (10 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
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// and w17, w18, ScratchpadL3Mask64
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emit32(0x121A0000 | 17 | (18 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
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// and w17, w20, ScratchpadL3Mask64
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emit32(0x121A0000 | 17 | (20 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
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codePos = PrologueSize;
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literalPos = ImulRcpLiteralsEnd;
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@ -148,16 +148,16 @@ void JitCompilerA64::generateProgram(Program& program, ProgramConfiguration& con
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}
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// Update spMix2
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// eor w18, config.readReg2, config.readReg3
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emit32(ARMV8A::EOR32 | 18 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
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// eor w20, config.readReg2, config.readReg3
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emit32(ARMV8A::EOR32 | 20 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
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// Jump back to the main loop
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const uint32_t offset = (((uint8_t*)randomx_program_aarch64_vm_instructions_end) - ((uint8_t*)randomx_program_aarch64)) - codePos;
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emit32(ARMV8A::B | (offset / 4), code, codePos);
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// and w18, w18, CacheLineAlignMask
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// and w20, w20, CacheLineAlignMask
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codePos = (((uint8_t*)randomx_program_aarch64_cacheline_align_mask1) - ((uint8_t*)randomx_program_aarch64));
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emit32(0x121A0000 | 18 | (18 << 5) | ((RandomX_CurrentConfig.Log2_DatasetBaseSize - 7) << 10), code, codePos);
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emit32(0x121A0000 | 20 | (20 << 5) | ((RandomX_CurrentConfig.Log2_DatasetBaseSize - 7) << 10), code, codePos);
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// and w10, w10, CacheLineAlignMask
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codePos = (((uint8_t*)randomx_program_aarch64_cacheline_align_mask2) - ((uint8_t*)randomx_program_aarch64));
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@ -189,8 +189,8 @@ void JitCompilerA64::generateProgramLight(Program& program, ProgramConfiguration
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// and w16, w10, ScratchpadL3Mask64
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emit32(0x121A0000 | 16 | (10 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
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// and w17, w18, ScratchpadL3Mask64
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emit32(0x121A0000 | 17 | (18 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
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// and w17, w20, ScratchpadL3Mask64
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emit32(0x121A0000 | 17 | (20 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
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codePos = PrologueSize;
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literalPos = ImulRcpLiteralsEnd;
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@ -206,8 +206,8 @@ void JitCompilerA64::generateProgramLight(Program& program, ProgramConfiguration
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}
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// Update spMix2
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// eor w18, config.readReg2, config.readReg3
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emit32(ARMV8A::EOR32 | 18 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
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// eor w20, config.readReg2, config.readReg3
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emit32(ARMV8A::EOR32 | 20 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
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// Jump back to the main loop
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const uint32_t offset = (((uint8_t*)randomx_program_aarch64_vm_instructions_end_light) - ((uint8_t*)randomx_program_aarch64)) - codePos;
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@ -477,7 +477,7 @@ void JitCompilerA64::emitAddImmediate(uint32_t dst, uint32_t src, uint32_t imm,
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}
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else
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{
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emitMovImmediate(tmp_reg, imm, code, k);
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// add dst, src, tmp_reg
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@ -526,7 +526,7 @@ void JitCompilerA64::emitMemLoadFP(uint32_t src, Instruction& instr, uint8_t* co
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uint32_t k = codePos;
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uint32_t imm = instr.getImm32();
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 19;
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imm &= instr.getModMem() ? (RandomX_CurrentConfig.ScratchpadL1_Size - 1) : (RandomX_CurrentConfig.ScratchpadL2_Size - 1);
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emitAddImmediate(tmp_reg, src, imm, code, k);
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@ -580,7 +580,7 @@ void JitCompilerA64::h_IADD_M(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emitMemLoad<tmp_reg>(dst, src, instr, code, k);
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// add dst, dst, tmp_reg
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@ -618,7 +618,7 @@ void JitCompilerA64::h_ISUB_M(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emitMemLoad<tmp_reg>(dst, src, instr, code, k);
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// sub dst, dst, tmp_reg
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@ -637,7 +637,7 @@ void JitCompilerA64::h_IMUL_R(Instruction& instr, uint32_t& codePos)
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if (src == dst)
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{
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src = 18;
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src = 20;
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emitMovImmediate(src, instr.getImm32(), code, k);
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}
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@ -655,7 +655,7 @@ void JitCompilerA64::h_IMUL_M(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emitMemLoad<tmp_reg>(dst, src, instr, code, k);
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// sub dst, dst, tmp_reg
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@ -686,7 +686,7 @@ void JitCompilerA64::h_IMULH_M(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emitMemLoad<tmp_reg>(dst, src, instr, code, k);
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// umulh dst, dst, tmp_reg
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@ -717,7 +717,7 @@ void JitCompilerA64::h_ISMULH_M(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emitMemLoad<tmp_reg>(dst, src, instr, code, k);
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// smulh dst, dst, tmp_reg
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@ -735,7 +735,7 @@ void JitCompilerA64::h_IMUL_RCP(Instruction& instr, uint32_t& codePos)
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uint32_t k = codePos;
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint64_t N = 1ULL << 63;
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@ -754,9 +754,9 @@ void JitCompilerA64::h_IMUL_RCP(Instruction& instr, uint32_t& codePos)
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literalPos -= sizeof(uint64_t);
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*(uint64_t*)(code + literalPos) = (q << shift) + ((r << shift) / divisor);
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if (literal_id < 13)
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if (literal_id < 12)
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{
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static constexpr uint32_t literal_regs[13] = { 30 << 16, 29 << 16, 28 << 16, 27 << 16, 26 << 16, 25 << 16, 24 << 16, 23 << 16, 22 << 16, 21 << 16, 20 << 16, 11 << 16, 0 };
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static constexpr uint32_t literal_regs[12] = { 30 << 16, 29 << 16, 28 << 16, 27 << 16, 26 << 16, 25 << 16, 24 << 16, 23 << 16, 22 << 16, 21 << 16, 11 << 16, 0 };
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// mul dst, dst, literal_reg
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emit32(ARMV8A::MUL | dst | (dst << 5) | literal_regs[literal_id], code, k);
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@ -794,7 +794,7 @@ void JitCompilerA64::h_IXOR_R(Instruction& instr, uint32_t& codePos)
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if (src == dst)
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{
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src = 18;
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src = 20;
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emitMovImmediate(src, instr.getImm32(), code, k);
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}
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@ -812,7 +812,7 @@ void JitCompilerA64::h_IXOR_M(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emitMemLoad<tmp_reg>(dst, src, instr, code, k);
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// eor dst, dst, tmp_reg
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@ -850,7 +850,7 @@ void JitCompilerA64::h_IROL_R(Instruction& instr, uint32_t& codePos)
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if (src != dst)
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{
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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// sub tmp_reg, xzr, src
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emit32(ARMV8A::SUB | tmp_reg | (31 << 5) | (src << 16), code, k);
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@ -878,7 +878,7 @@ void JitCompilerA64::h_ISWAP_R(Instruction& instr, uint32_t& codePos)
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uint32_t k = codePos;
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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emit32(ARMV8A::MOV_REG | tmp_reg | (dst << 16), code, k);
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emit32(ARMV8A::MOV_REG | dst | (src << 16), code, k);
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emit32(ARMV8A::MOV_REG | src | (tmp_reg << 16), code, k);
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@ -1026,7 +1026,7 @@ void JitCompilerA64::h_CFROUND(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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constexpr uint32_t fpcr_tmp_reg = 8;
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// ror tmp_reg, src, imm
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@ -1050,7 +1050,7 @@ void JitCompilerA64::h_ISTORE(Instruction& instr, uint32_t& codePos)
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const uint32_t src = IntRegMap[instr.src];
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const uint32_t dst = IntRegMap[instr.dst];
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constexpr uint32_t tmp_reg = 18;
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constexpr uint32_t tmp_reg = 20;
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uint32_t imm = instr.getImm32();
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@ -72,9 +72,9 @@
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# x15 -> "r7"
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# x16 -> spAddr0
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# x17 -> spAddr1
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# x18 -> temporary
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# x18 -> unused (platform register, don't touch it)
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# x19 -> temporary
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# x20 -> literal for IMUL_RCP
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# x20 -> temporary
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# x21 -> literal for IMUL_RCP
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# x22 -> literal for IMUL_RCP
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# x23 -> literal for IMUL_RCP
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@ -109,7 +109,7 @@ DECL(randomx_program_aarch64):
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# Save callee-saved registers
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sub sp, sp, 192
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stp x16, x17, [sp]
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stp x18, x19, [sp, 16]
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str x19, [sp, 16]
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stp x20, x21, [sp, 32]
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stp x22, x23, [sp, 48]
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stp x24, x25, [sp, 64]
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@ -164,7 +164,6 @@ DECL(randomx_program_aarch64):
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# Read literals
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ldr x0, literal_x0
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ldr x11, literal_x11
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ldr x20, literal_x20
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ldr x21, literal_x21
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ldr x22, literal_x22
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ldr x23, literal_x23
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@ -196,11 +195,11 @@ DECL(randomx_program_aarch64):
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DECL(randomx_program_aarch64_main_loop):
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# spAddr0 = spMix1 & ScratchpadL3Mask64;
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# spAddr1 = (spMix1 >> 32) & ScratchpadL3Mask64;
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lsr x18, x10, 32
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lsr x20, x10, 32
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# Actual mask will be inserted by JIT compiler
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and w16, w10, 1
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and w17, w18, 1
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and w17, w20, 1
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# x16 = scratchpad + spAddr0
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# x17 = scratchpad + spAddr1
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@ -208,31 +207,31 @@ DECL(randomx_program_aarch64_main_loop):
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add x17, x17, x2
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# xor integer registers with scratchpad data (spAddr0)
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ldp x18, x19, [x16]
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eor x4, x4, x18
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ldp x20, x19, [x16]
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eor x4, x4, x20
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eor x5, x5, x19
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ldp x18, x19, [x16, 16]
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eor x6, x6, x18
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ldp x20, x19, [x16, 16]
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eor x6, x6, x20
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eor x7, x7, x19
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ldp x18, x19, [x16, 32]
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eor x12, x12, x18
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ldp x20, x19, [x16, 32]
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eor x12, x12, x20
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eor x13, x13, x19
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ldp x18, x19, [x16, 48]
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eor x14, x14, x18
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ldp x20, x19, [x16, 48]
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eor x14, x14, x20
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eor x15, x15, x19
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# Load group F registers (spAddr1)
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ldpsw x18, x19, [x17]
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ins v16.d[0], x18
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ldpsw x20, x19, [x17]
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ins v16.d[0], x20
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ins v16.d[1], x19
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ldpsw x18, x19, [x17, 8]
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ins v17.d[0], x18
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ldpsw x20, x19, [x17, 8]
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ins v17.d[0], x20
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ins v17.d[1], x19
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ldpsw x18, x19, [x17, 16]
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ins v18.d[0], x18
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ldpsw x20, x19, [x17, 16]
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ins v18.d[0], x20
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ins v18.d[1], x19
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ldpsw x18, x19, [x17, 24]
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ins v19.d[0], x18
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ldpsw x20, x19, [x17, 24]
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ins v19.d[0], x20
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ins v19.d[1], x19
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scvtf v16.2d, v16.2d
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scvtf v17.2d, v17.2d
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@ -240,17 +239,17 @@ DECL(randomx_program_aarch64_main_loop):
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scvtf v19.2d, v19.2d
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# Load group E registers (spAddr1)
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ldpsw x18, x19, [x17, 32]
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ins v20.d[0], x18
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ldpsw x20, x19, [x17, 32]
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ins v20.d[0], x20
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ins v20.d[1], x19
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ldpsw x18, x19, [x17, 40]
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ins v21.d[0], x18
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ldpsw x20, x19, [x17, 40]
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ins v21.d[0], x20
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ins v21.d[1], x19
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ldpsw x18, x19, [x17, 48]
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ins v22.d[0], x18
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ldpsw x20, x19, [x17, 48]
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ins v22.d[0], x20
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ins v22.d[1], x19
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ldpsw x18, x19, [x17, 56]
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ins v23.d[0], x18
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ldpsw x20, x19, [x17, 56]
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ins v23.d[0], x20
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ins v23.d[1], x19
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scvtf v20.2d, v20.2d
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scvtf v21.2d, v21.2d
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@ -273,7 +272,6 @@ DECL(randomx_program_aarch64_vm_instructions):
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literal_x0: .fill 1,8,0
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literal_x11: .fill 1,8,0
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literal_x20: .fill 1,8,0
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literal_x21: .fill 1,8,0
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literal_x22: .fill 1,8,0
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literal_x23: .fill 1,8,0
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@ -309,17 +307,17 @@ DECL(randomx_program_aarch64_vm_instructions_end):
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lsr x10, x9, 32
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# mx ^= r[readReg2] ^ r[readReg3];
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eor x9, x9, x18
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eor x9, x9, x20
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# Calculate dataset pointer for dataset prefetch
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mov w18, w9
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mov w20, w9
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DECL(randomx_program_aarch64_cacheline_align_mask1):
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# Actual mask will be inserted by JIT compiler
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and x18, x18, 1
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add x18, x18, x1
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and x20, x20, 1
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add x20, x20, x1
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# Prefetch dataset data
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prfm pldl2strm, [x18]
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prfm pldl2strm, [x20]
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# mx <-> ma
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ror x9, x9, 32
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@ -331,17 +329,17 @@ DECL(randomx_program_aarch64_cacheline_align_mask2):
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DECL(randomx_program_aarch64_xor_with_dataset_line):
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# xor integer registers with dataset data
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ldp x18, x19, [x10]
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eor x4, x4, x18
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ldp x20, x19, [x10]
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eor x4, x4, x20
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eor x5, x5, x19
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ldp x18, x19, [x10, 16]
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eor x6, x6, x18
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ldp x20, x19, [x10, 16]
|
||||
eor x6, x6, x20
|
||||
eor x7, x7, x19
|
||||
ldp x18, x19, [x10, 32]
|
||||
eor x12, x12, x18
|
||||
ldp x20, x19, [x10, 32]
|
||||
eor x12, x12, x20
|
||||
eor x13, x13, x19
|
||||
ldp x18, x19, [x10, 48]
|
||||
eor x14, x14, x18
|
||||
ldp x20, x19, [x10, 48]
|
||||
eor x14, x14, x20
|
||||
eor x15, x15, x19
|
||||
|
||||
DECL(randomx_program_aarch64_update_spMix1):
|
||||
|
|
@ -384,7 +382,7 @@ DECL(randomx_program_aarch64_update_spMix1):
|
|||
|
||||
# Restore callee-saved registers
|
||||
ldp x16, x17, [sp]
|
||||
ldp x18, x19, [sp, 16]
|
||||
ldr x19, [sp, 16]
|
||||
ldp x20, x21, [sp, 32]
|
||||
ldp x22, x23, [sp, 48]
|
||||
ldp x24, x25, [sp, 64]
|
||||
|
|
@ -405,7 +403,7 @@ DECL(randomx_program_aarch64_vm_instructions_end_light):
|
|||
stp x2, x30, [sp, 80]
|
||||
|
||||
# mx ^= r[readReg2] ^ r[readReg3];
|
||||
eor x9, x9, x18
|
||||
eor x9, x9, x20
|
||||
|
||||
# mx <-> ma
|
||||
ror x9, x9, 32
|
||||
|
|
@ -447,8 +445,8 @@ DECL(randomx_program_aarch64_light_dataset_offset):
|
|||
# x3 -> end item
|
||||
|
||||
DECL(randomx_init_dataset_aarch64):
|
||||
# Save x30 (return address)
|
||||
str x30, [sp, -16]!
|
||||
# Save x20 (used as temporary, but must be saved to not break ABI) and x30 (return address)
|
||||
stp x20, x30, [sp, -16]!
|
||||
|
||||
# Load pointer to cache memory
|
||||
ldr x0, [x0]
|
||||
|
|
@ -460,8 +458,8 @@ DECL(randomx_init_dataset_aarch64_main_loop):
|
|||
cmp x2, x3
|
||||
bne DECL(randomx_init_dataset_aarch64_main_loop)
|
||||
|
||||
# Restore x30 (return address)
|
||||
ldr x30, [sp], 16
|
||||
# Restore x20 and x30
|
||||
ldp x20, x30, [sp], 16
|
||||
|
||||
ret
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue