From fc82cf1cf21b4f0aadb867e31efb26a1bad69686 Mon Sep 17 00:00:00 2001
From: XMRig <support@xmrig.com>
Date: Mon, 5 Mar 2018 02:15:05 +0700
Subject: [PATCH] #428 Fixed regression with CPU cache size detection.

---
 src/Cpu.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/Cpu.cpp b/src/Cpu.cpp
index a619781e0..eba993b37 100644
--- a/src/Cpu.cpp
+++ b/src/Cpu.cpp
@@ -100,9 +100,9 @@ void Cpu::initCommon()
         m_l2_cache = data.l2_cache * (m_totalCores / 2) * m_sockets;
         m_l2_exclusive = true;
     }
-    // Workaround for Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue
+    // Workaround for Intel Pentium Dual-Core, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue
     // These processors have L2 cache shared by 2 cores.
-    else if (data.vendor == VENDOR_INTEL && data.family == 0x06 && (data.model == 0x0E || data.model == 0x0F || data.model == 0x07)) {
+    else if (data.vendor == VENDOR_INTEL && data.ext_family == 0x06 && (data.ext_model == 0x0E || data.ext_model == 0x0F || data.ext_model == 0x17)) {
         int l2_count_per_socket = m_totalCores > 1 ? m_totalCores / 2 : 1;
         m_l2_cache = data.l2_cache > 0 ? data.l2_cache * l2_count_per_socket * m_sockets : 0;
     }