mirror of
https://github.com/xmrig/xmrig.git
synced 2024-12-23 03:59:41 +00:00
RandomX: added cache QoS support
False by default. If set to true, all non-mining CPU cores will not have access to L3 cache.
This commit is contained in:
parent
e5a2689052
commit
c83429c55c
10 changed files with 126 additions and 19 deletions
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@ -62,6 +62,7 @@ public:
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FLAG_SSSE3,
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FLAG_XOP,
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FLAG_POPCNT,
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FLAG_CAT_L3,
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FLAG_MAX
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};
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@ -79,6 +80,7 @@ public:
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virtual bool hasAVX2() const = 0;
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virtual bool hasBMI2() const = 0;
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virtual bool hasOneGbPages() const = 0;
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virtual bool hasCatL3() const = 0;
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virtual const char *backend() const = 0;
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virtual const char *brand() const = 0;
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virtual CpuThreads threads(const Algorithm &algorithm, uint32_t limit) const = 0;
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@ -57,7 +57,7 @@
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namespace xmrig {
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static const std::array<const char *, ICpuInfo::FLAG_MAX> flagNames = { "aes", "avx2", "avx512f", "bmi2", "osxsave", "pdpe1gb", "sse2", "ssse3", "xop", "popcnt" };
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static const std::array<const char *, ICpuInfo::FLAG_MAX> flagNames = { "aes", "avx2", "avx512f", "bmi2", "osxsave", "pdpe1gb", "sse2", "ssse3", "xop", "popcnt", "cat_l3" };
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static const std::array<const char *, ICpuInfo::MSR_MOD_MAX> msrNames = { "none", "ryzen", "intel", "custom" };
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@ -66,7 +66,7 @@ static inline void cpuid(uint32_t level, int32_t output[4])
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memset(output, 0, sizeof(int32_t) * 4);
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# ifdef _MSC_VER
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__cpuid(output, static_cast<int>(level));
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__cpuidex(output, static_cast<int>(level), 0);
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# else
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__cpuid_count(level, 0, output[0], output[1], output[2], output[3]);
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# endif
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@ -143,6 +143,7 @@ static inline bool has_sse2() { return has_feature(PROCESSOR_INFO,
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static inline bool has_ssse3() { return has_feature(PROCESSOR_INFO, ECX_Reg, 1 << 9); }
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static inline bool has_xop() { return has_feature(0x80000001, ECX_Reg, 1 << 11); }
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static inline bool has_popcnt() { return has_feature(PROCESSOR_INFO, ECX_Reg, 1 << 23); }
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static inline bool has_cat_l3() { return has_feature(EXTENDED_FEATURES, EBX_Reg, 1 << 15) && has_feature(0x10, EBX_Reg, 1 << 1); }
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} // namespace xmrig
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@ -178,6 +179,7 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
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m_flags.set(FLAG_SSSE3, has_ssse3());
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m_flags.set(FLAG_XOP, has_xop());
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m_flags.set(FLAG_POPCNT, has_popcnt());
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m_flags.set(FLAG_CAT_L3, has_cat_l3());
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# ifdef XMRIG_FEATURE_ASM
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if (hasAES()) {
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@ -51,6 +51,7 @@ protected:
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inline bool hasAVX2() const override { return has(FLAG_AVX2); }
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inline bool hasBMI2() const override { return has(FLAG_BMI2); }
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inline bool hasOneGbPages() const override { return has(FLAG_PDPE1GB); }
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inline bool hasCatL3() const override { return has(FLAG_CAT_L3); }
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inline const char *brand() const override { return m_brand; }
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inline MsrMod msrMod() const override { return m_msrMod; }
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inline size_t cores() const override { return 0; }
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@ -20,6 +20,7 @@
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"1gb-pages": false,
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"rdmsr": true,
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"wrmsr": true,
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"cache_qos": false,
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"numa": true
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},
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"cpu": {
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@ -28,6 +28,7 @@
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#include "crypto/rx/Rx.h"
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#include "backend/common/Tags.h"
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#include "backend/cpu/CpuConfig.h"
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#include "backend/cpu/CpuThreads.h"
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#include "base/io/log/Log.h"
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#include "base/io/log/Tags.h"
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#include "crypto/rx/RxConfig.h"
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@ -78,7 +79,7 @@ bool xmrig::Rx::init(const Job &job, const RxConfig &config, const CpuConfig &cp
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}
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if (!msrInitialized) {
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msrInit(config);
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msrInit(config, cpu.threads().get(job.algorithm()).data());
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msrInitialized = true;
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}
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@ -30,6 +30,7 @@
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#include <cstdint>
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#include <utility>
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#include <vector>
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#include "crypto/common/HugePagesInfo.h"
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@ -41,6 +42,7 @@ namespace xmrig
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class Algorithm;
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class CpuConfig;
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class CpuThread;
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class IRxListener;
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class Job;
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class RxConfig;
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@ -62,7 +64,7 @@ public:
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# endif
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private:
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static void msrInit(const RxConfig &config);
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static void msrInit(const RxConfig &config, const std::vector<CpuThread>& threads);
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static void msrDestroy();
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static void setupMainLoopExceptionFrame();
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};
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@ -51,6 +51,7 @@ static const char *kMode = "mode";
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static const char *kOneGbPages = "1gb-pages";
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static const char *kRdmsr = "rdmsr";
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static const char *kWrmsr = "wrmsr";
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static const char *kCacheQoS = "cache_qos";
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#ifdef XMRIG_FEATURE_HWLOC
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static const char *kNUMA = "numa";
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@ -89,6 +90,8 @@ bool xmrig::RxConfig::read(const rapidjson::Value &value)
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readMSR(Json::getValue(value, kWrmsr));
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# endif
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m_cacheQoS = Json::getBool(value, kCacheQoS, m_cacheQoS);
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# ifdef XMRIG_OS_LINUX
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m_oneGbPages = Json::getBool(value, kOneGbPages, m_oneGbPages);
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# endif
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@ -151,6 +154,8 @@ rapidjson::Value xmrig::RxConfig::toJSON(rapidjson::Document &doc) const
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obj.AddMember(StringRef(kWrmsr), false, allocator);
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# endif
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obj.AddMember(StringRef(kCacheQoS), m_cacheQoS, allocator);
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# ifdef XMRIG_FEATURE_HWLOC
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if (!m_nodeset.empty()) {
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Value numa(kArrayType);
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@ -65,6 +65,7 @@ public:
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inline bool isOneGbPages() const { return m_oneGbPages; }
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inline bool rdmsr() const { return m_rdmsr; }
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inline bool wrmsr() const { return m_wrmsr; }
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inline bool cacheQoS() const { return m_cacheQoS; }
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inline Mode mode() const { return m_mode; }
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# ifdef XMRIG_FEATURE_MSR
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@ -83,6 +84,8 @@ private:
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bool m_wrmsr = false;
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# endif
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bool m_cacheQoS = false;
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Mode readMode(const rapidjson::Value &value) const;
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bool m_numa = true;
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@ -29,6 +29,7 @@
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#include "crypto/rx/Rx.h"
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#include "backend/cpu/Cpu.h"
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#include "backend/cpu/CpuThread.h"
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#include "base/io/log/Log.h"
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#include "base/tools/Chrono.h"
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#include "crypto/rx/RxConfig.h"
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@ -123,14 +124,15 @@ static bool wrmsr_on_cpu(uint32_t reg, uint32_t cpu, uint64_t value, uint64_t ma
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}
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static bool wrmsr_on_all_cpus(uint32_t reg, uint64_t value, uint64_t mask)
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template<typename T>
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static bool wrmsr_on_all_cpus(uint32_t reg, uint64_t value, uint64_t mask, T&& callback)
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{
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struct dirent **namelist;
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int dir_entries = scandir("/dev/cpu", &namelist, dir_filter, 0);
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int errors = 0;
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while (dir_entries--) {
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if (!wrmsr_on_cpu(reg, strtoul(namelist[dir_entries]->d_name, nullptr, 10), value, mask)) {
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if (!callback(reg, strtoul(namelist[dir_entries]->d_name, nullptr, 10), value, mask)) {
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++errors;
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}
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@ -159,7 +161,7 @@ static bool wrmsr_modprobe()
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}
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static bool wrmsr(const MsrItems &preset, bool save)
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static bool wrmsr(const MsrItems& preset, const std::vector<CpuThread>& threads, bool cache_qos, bool save)
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{
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if (!wrmsr_modprobe()) {
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return false;
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@ -177,12 +179,61 @@ static bool wrmsr(const MsrItems &preset, bool save)
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}
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for (const auto &i : preset) {
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if (!wrmsr_on_all_cpus(i.reg(), i.value(), i.mask())) {
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if (!wrmsr_on_all_cpus(i.reg(), i.value(), i.mask(), [](uint32_t reg, uint32_t cpu, uint64_t value, uint64_t mask) { return wrmsr_on_cpu(reg, cpu, value, mask); })) {
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return false;
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}
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}
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return true;
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const uint32_t n = Cpu::info()->threads();
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// Which CPU cores will have access to the full L3 cache
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std::vector<bool> cacheEnabled(n, false);
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bool cacheQoSDisabled = threads.empty();
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for (const CpuThread& t : threads) {
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// If some thread has no affinity or wrong affinity, disable cache QoS
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if ((t.affinity() < 0) || (t.affinity() >= n)) {
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cacheQoSDisabled = true;
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if (cache_qos) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "Cache QoS can only be enabled when all mining threads have affinity set", tag);
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}
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break;
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}
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cacheEnabled[t.affinity()] = true;
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}
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if (cache_qos && !Cpu::info()->hasCatL3()) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "This CPU doesn't support cat_l3, cache QoS is unavailable", tag);
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cache_qos = false;
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}
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bool result = true;
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if (cache_qos) {
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result = wrmsr_on_all_cpus(0xC8F, 0, MsrItem::kNoMask, [&cacheEnabled, cacheQoSDisabled](uint32_t, uint32_t cpu, uint64_t, uint64_t) {
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if (cacheQoSDisabled || (cpu >= cacheEnabled.size()) || cacheEnabled[cpu]) {
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// Assign Class Of Service 0 to current CPU core (default, full L3 cache available)
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if (!wrmsr_on_cpu(0xC8F, cpu, 0, MsrItem::kNoMask)) {
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return false;
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}
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}
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else {
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// Disable L3 cache for Class Of Service 1
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if (!wrmsr_on_cpu(0xC91, cpu, 0, MsrItem::kNoMask)) {
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return false;
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}
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// Assign Class Of Service 1 to current CPU core
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if (!wrmsr_on_cpu(0xC8F, cpu, 1ULL << 32, MsrItem::kNoMask)) {
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return false;
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}
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}
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return true;
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});
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}
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return result;
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}
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} // namespace xmrig
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void xmrig::Rx::msrInit(const RxConfig &config)
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void xmrig::Rx::msrInit(const RxConfig &config, const std::vector<CpuThread>& threads)
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{
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const auto &preset = config.msrPreset();
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if (preset.empty()) {
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@ -225,7 +276,7 @@ void xmrig::Rx::msrInit(const RxConfig &config)
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const uint64_t ts = Chrono::steadyMSecs();
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if (wrmsr(preset, config.rdmsr())) {
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if (wrmsr(preset, threads, config.cacheQoS(), config.rdmsr())) {
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LOG_NOTICE(CLEAR "%s" GREEN_BOLD_S "register values for \"%s\" preset has been set successfully" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, config.msrPresetName(), Chrono::steadyMSecs() - ts);
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}
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else {
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const uint64_t ts = Chrono::steadyMSecs();
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if (!wrmsr(savedState, false)) {
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if (!wrmsr(savedState, std::vector<CpuThread>(), true, false)) {
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LOG_ERR(CLEAR "%s" RED_BOLD_S "failed to restore initial state" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, Chrono::steadyMSecs() - ts);
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}
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}
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@ -30,6 +30,7 @@
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#include "crypto/rx/Rx.h"
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#include "backend/cpu/Cpu.h"
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#include "backend/cpu/CpuThread.h"
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#include "base/io/log/Log.h"
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#include "base/kernel/Platform.h"
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#include "base/tools/Chrono.h"
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@ -256,7 +257,7 @@ static bool wrmsr(HANDLE driver, uint32_t reg, uint64_t value, uint64_t mask)
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}
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static bool wrmsr(const MsrItems &preset, bool save)
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static bool wrmsr(const MsrItems &preset, const std::vector<CpuThread>& threads, bool cache_qos, bool save)
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{
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bool success = true;
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@ -282,14 +283,52 @@ static bool wrmsr(const MsrItems &preset, bool save)
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}
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}
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std::thread wrmsr_thread([driver, &preset, &success]() {
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for (uint32_t i = 0, n = Cpu::info()->threads(); i < n; ++i) {
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const uint32_t n = Cpu::info()->threads();
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// Which CPU cores will have access to the full L3 cache
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std::vector<bool> cacheEnabled(n, false);
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bool cacheQoSDisabled = threads.empty();
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for (const CpuThread& t : threads) {
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// If some thread has no affinity or wrong affinity, disable cache QoS
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if ((t.affinity() < 0) || (t.affinity() >= n)) {
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cacheQoSDisabled = true;
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if (cache_qos) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "Cache QoS can only be enabled when all mining threads have affinity set", tag);
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}
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break;
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}
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cacheEnabled[t.affinity()] = true;
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}
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if (cache_qos && !Cpu::info()->hasCatL3()) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "This CPU doesn't support cat_l3, cache QoS is unavailable", tag);
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cache_qos = false;
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}
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std::thread wrmsr_thread([n, driver, &preset, &cacheEnabled, cache_qos, cacheQoSDisabled, &success]() {
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for (uint32_t i = 0; i < n; ++i) {
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if (!Platform::setThreadAffinity(i)) {
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continue;
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}
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for (const auto &i : preset) {
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success = wrmsr(driver, i.reg(), i.value(), i.mask());
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success &= wrmsr(driver, i.reg(), i.value(), i.mask());
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}
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if (cache_qos) {
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if (cacheQoSDisabled || cacheEnabled[i]) {
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// Assign Class Of Service 0 to current CPU core (default, full L3 cache available)
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success &= wrmsr(driver, 0xC8F, 0, MsrItem::kNoMask);
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}
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else {
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// Disable L3 cache for Class Of Service 1
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success &= wrmsr(driver, 0xC91, 0, MsrItem::kNoMask);
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// Assign Class Of Service 1 to current CPU core
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success &= wrmsr(driver, 0xC8F, 1ULL << 32, MsrItem::kNoMask);
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}
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}
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if (!success) {
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@ -349,7 +388,7 @@ void Rx::setMainLoopBounds(const std::pair<const void*, const void*>& bounds)
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} // namespace xmrig
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void xmrig::Rx::msrInit(const RxConfig &config)
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void xmrig::Rx::msrInit(const RxConfig &config, const std::vector<CpuThread>& threads)
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{
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const auto &preset = config.msrPreset();
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if (preset.empty()) {
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const uint64_t ts = Chrono::steadyMSecs();
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if (wrmsr(preset, config.rdmsr())) {
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if (wrmsr(preset, threads, config.cacheQoS(), config.rdmsr())) {
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LOG_NOTICE(CLEAR "%s" GREEN_BOLD_S "register values for \"%s\" preset has been set successfully" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, config.msrPresetName(), Chrono::steadyMSecs() - ts);
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}
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else {
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const uint64_t ts = Chrono::steadyMSecs();
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if (!wrmsr(savedState, false)) {
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if (!wrmsr(savedState, std::vector<CpuThread>(), true, false)) {
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LOG_ERR(CLEAR "%s" RED_BOLD_S "failed to restore initial state" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, Chrono::steadyMSecs() - ts);
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}
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}
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