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https://github.com/xmrig/xmrig.git
synced 2024-11-18 18:11:05 +00:00
Fixed wrong ASM code alignment on macOS, thanks @SChernykh.
This commit is contained in:
parent
59b147b6fb
commit
a98c475a3c
11 changed files with 26 additions and 22 deletions
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@ -94,7 +94,7 @@
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lea r9, QWORD PTR [rdx+r13]
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movdqu xmm15, XMMWORD PTR [r9]
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ALIGN 16
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ALIGN(64)
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main_loop_double_sandybridge:
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movdqu xmm9, xmm15
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mov eax, edx
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@ -45,7 +45,7 @@
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movq xmm0, rcx
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punpcklqdq xmm4, xmm0
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ALIGN 16
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ALIGN(64)
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cnv2_main_loop_bulldozer:
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movdqa xmm5, XMMWORD PTR [r10+rbx]
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movq xmm6, r8
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@ -50,7 +50,7 @@
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punpcklqdq xmm5, xmm0
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movdqu xmm6, XMMWORD PTR [r10+rbx]
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ALIGN 16
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ALIGN(64)
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main_loop_ivybridge:
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lea rdx, QWORD PTR [r10+rbx]
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mov ecx, r10d
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@ -45,7 +45,7 @@
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movq xmm0, rcx
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punpcklqdq xmm4, xmm0
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ALIGN 16
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ALIGN(64)
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main_loop_ryzen:
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movdqa xmm5, XMMWORD PTR [r10+rbx]
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movq xmm0, r11
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@ -1,4 +1,8 @@
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#define ALIGN .align
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#ifdef __APPLE__
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# define ALIGN(x) .align 6
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#else
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# define ALIGN(x) .align 64
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#endif
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.intel_syntax noprefix
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#ifdef __APPLE__
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# define FN_PREFIX(fn) _ ## fn
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@ -12,7 +16,7 @@
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.global FN_PREFIX(cnv2_mainloop_bulldozer_asm)
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.global FN_PREFIX(cnv2_double_mainloop_sandybridge_asm)
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ALIGN 16
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ALIGN(64)
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FN_PREFIX(cnv2_mainloop_ivybridge_asm):
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sub rsp, 48
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mov rcx, rdi
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@ -24,7 +28,7 @@ FN_PREFIX(cnv2_mainloop_ivybridge_asm):
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nop
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nop
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ALIGN 16
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ALIGN(64)
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FN_PREFIX(cnv2_mainloop_ryzen_asm):
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sub rsp, 48
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mov rcx, rdi
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@ -36,7 +40,7 @@ FN_PREFIX(cnv2_mainloop_ryzen_asm):
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nop
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nop
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ALIGN 16
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ALIGN(64)
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FN_PREFIX(cnv2_mainloop_bulldozer_asm):
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sub rsp, 48
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mov rcx, rdi
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@ -48,7 +52,7 @@ FN_PREFIX(cnv2_mainloop_bulldozer_asm):
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nop
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nop
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ALIGN 16
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ALIGN(64)
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FN_PREFIX(cnv2_double_mainloop_sandybridge_asm):
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sub rsp, 48
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mov rcx, rdi
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@ -4,7 +4,7 @@ PUBLIC cnv2_mainloop_ryzen_asm
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PUBLIC cnv2_mainloop_bulldozer_asm
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PUBLIC cnv2_double_mainloop_sandybridge_asm
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ALIGN 64
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ALIGN(64)
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cnv2_mainloop_ivybridge_asm PROC
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INCLUDE cn2/cnv2_main_loop_ivybridge.inc
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ret 0
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@ -14,7 +14,7 @@ cnv2_mainloop_ivybridge_asm PROC
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nop
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cnv2_mainloop_ivybridge_asm ENDP
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ALIGN 64
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ALIGN(64)
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cnv2_mainloop_ryzen_asm PROC
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INCLUDE cn2/cnv2_main_loop_ryzen.inc
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ret 0
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@ -24,7 +24,7 @@ cnv2_mainloop_ryzen_asm PROC
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nop
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cnv2_mainloop_ryzen_asm ENDP
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ALIGN 64
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ALIGN(64)
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cnv2_mainloop_bulldozer_asm PROC
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INCLUDE cn2/cnv2_main_loop_bulldozer.inc
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ret 0
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@ -34,7 +34,7 @@ cnv2_mainloop_bulldozer_asm PROC
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nop
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cnv2_mainloop_bulldozer_asm ENDP
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ALIGN 64
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ALIGN(64)
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cnv2_double_mainloop_sandybridge_asm PROC
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INCLUDE cn2/cnv2_double_main_loop_sandybridge.inc
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ret 0
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@ -94,7 +94,7 @@
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lea r9, QWORD PTR [rdx+r13]
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movdqu xmm15, XMMWORD PTR [r9]
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ALIGN 16
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ALIGN(64)
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main_loop_double_sandybridge:
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movdqu xmm9, xmm15
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mov eax, edx
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@ -45,7 +45,7 @@
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movd xmm0, rcx
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punpcklqdq xmm4, xmm0
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ALIGN 16
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ALIGN(64)
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cnv2_main_loop_bulldozer:
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movdqa xmm5, XMMWORD PTR [r10+rbx]
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movd xmm6, r8
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@ -50,7 +50,7 @@
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punpcklqdq xmm5, xmm0
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movdqu xmm6, XMMWORD PTR [r10+rbx]
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ALIGN 16
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ALIGN(64)
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main_loop_ivybridge:
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lea rdx, QWORD PTR [r10+rbx]
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mov ecx, r10d
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@ -45,7 +45,7 @@
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movd xmm0, rcx
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punpcklqdq xmm4, xmm0
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ALIGN 16
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ALIGN(64)
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main_loop_ryzen:
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movdqa xmm5, XMMWORD PTR [r10+rbx]
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movd xmm0, r11
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@ -1,4 +1,4 @@
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#define ALIGN .align
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#define ALIGN(x) .align 64
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.intel_syntax noprefix
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.section .text
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.global cnv2_mainloop_ivybridge_asm
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@ -6,7 +6,7 @@
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.global cnv2_mainloop_bulldozer_asm
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.global cnv2_double_mainloop_sandybridge_asm
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ALIGN 16
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ALIGN(64)
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cnv2_mainloop_ivybridge_asm:
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#include "../cn2/cnv2_main_loop_ivybridge.inc"
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ret 0
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@ -15,7 +15,7 @@ cnv2_mainloop_ivybridge_asm:
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nop
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nop
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ALIGN 16
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ALIGN(64)
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cnv2_mainloop_ryzen_asm:
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#include "../cn2/cnv2_main_loop_ryzen.inc"
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ret 0
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@ -24,7 +24,7 @@ cnv2_mainloop_ryzen_asm:
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nop
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nop
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ALIGN 16
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ALIGN(64)
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cnv2_mainloop_bulldozer_asm:
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#include "../cn2/cnv2_main_loop_bulldozer.inc"
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ret 0
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@ -33,7 +33,7 @@ cnv2_mainloop_bulldozer_asm:
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nop
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nop
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ALIGN 16
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ALIGN(64)
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cnv2_double_mainloop_sandybridge_asm:
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#include "../cn2/cnv2_double_main_loop_sandybridge.inc"
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ret 0
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