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https://github.com/xmrig/xmrig.git
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Added save/restore MSR registers on Linux.
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parent
9cea70b77c
commit
a877b1d269
2 changed files with 56 additions and 53 deletions
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@ -48,16 +48,8 @@
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namespace xmrig {
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enum MsrMod : uint32_t {
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MSR_MOD_NONE,
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MSR_MOD_RYZEN,
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MSR_MOD_INTEL,
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MSR_MOD_MAX
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};
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static const char *tag = YELLOW_BG_BOLD(WHITE_BOLD_S " msr ") " ";
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static const std::array<const char *, MSR_MOD_MAX> modNames = { nullptr, "Ryzen", "Intel" };
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static const char *tag = YELLOW_BG_BOLD(WHITE_BOLD_S " msr ") " ";
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static MsrItems savedState;
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static inline int dir_filter(const struct dirent *dirp)
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@ -108,6 +100,37 @@ static bool wrmsr_on_all_cpus(uint32_t reg, uint64_t value)
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}
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bool rdmsr_on_cpu(uint32_t reg, uint32_t cpu, uint64_t &value)
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{
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char msr_file_name[64]{};
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sprintf(msr_file_name, "/dev/cpu/%u/msr", cpu);
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int fd = open(msr_file_name, O_RDONLY);
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if (fd < 0) {
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return false;
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}
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const bool success = pread(fd, &value, sizeof value, reg) == sizeof value;
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close(fd);
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return success;
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}
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static MsrItem rdmsr(uint32_t reg)
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{
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uint64_t value = 0;
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if (!rdmsr_on_cpu(reg, 0, value)) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "cannot read MSR 0x%08" PRIx32, tag, reg);
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return {};
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}
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return { reg, value };
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}
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static bool wrmsr_modprobe()
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{
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if (system("/sbin/modprobe msr > /dev/null 2>&1") != 0) {
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@ -120,12 +143,21 @@ static bool wrmsr_modprobe()
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}
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static bool wrmsr(const MsrItems &preset)
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static bool wrmsr(const MsrItems &preset, bool save)
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{
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if (!wrmsr_modprobe()) {
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return false;
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}
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if (save) {
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for (const auto &i : preset) {
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auto item = rdmsr(i.reg());
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if (item.isValid()) {
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savedState.emplace_back(item);
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}
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}
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}
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for (const auto &i : preset) {
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if (!wrmsr_on_all_cpus(i.reg(), i.value())) {
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return false;
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@ -148,46 +180,21 @@ void xmrig::Rx::msrInit(const RxConfig &config)
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const uint64_t ts = Chrono::steadyMSecs();
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if (wrmsr(preset)) {
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if (wrmsr(preset, config.rdmsr())) {
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LOG_NOTICE(CLEAR "%s" GREEN_BOLD_S "register values for \"%s\" preset has been set successfully" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, config.msrPresetName(), Chrono::steadyMSecs() - ts);
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}
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// if (config.wrmsr() < 0) {
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// return;
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// }
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// MsrMod mod = MSR_MOD_NONE;
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// if (Cpu::info()->assembly() == Assembly::RYZEN) {
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// mod = MSR_MOD_RYZEN;
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// }
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// else if (Cpu::info()->vendor() == ICpuInfo::VENDOR_INTEL) {
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// mod = MSR_MOD_INTEL;
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// }
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// if (mod == MSR_MOD_NONE) {
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// return;
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// }
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// const uint64_t ts = Chrono::steadyMSecs();
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// if (!wrmsr_modprobe()) {
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// return;
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// }
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// if (mod == MSR_MOD_RYZEN) {
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// wrmsr_on_all_cpus(0xC0011020, 0);
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// wrmsr_on_all_cpus(0xC0011021, 0x40);
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// wrmsr_on_all_cpus(0xC0011022, 0x510000);
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// wrmsr_on_all_cpus(0xC001102b, 0x1808cc16);
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// }
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// else if (mod == MSR_MOD_INTEL) {
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// wrmsr_on_all_cpus(0x1a4, config.wrmsr());
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// }
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// LOG_NOTICE(CLEAR "%s" GREEN_BOLD_S "register values for %s has been set successfully" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, modNames[mod], Chrono::steadyMSecs() - ts);
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}
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void xmrig::Rx::msrDestroy()
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{
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if (savedState.empty()) {
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return;
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}
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const uint64_t ts = Chrono::steadyMSecs();
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if (!wrmsr(savedState, false)) {
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LOG_ERR(CLEAR "%s" RED_BOLD_S "failed to restore initial state" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, Chrono::steadyMSecs() - ts);
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}
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}
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@ -211,13 +211,7 @@ static bool rdmsr(HANDLE driver, uint32_t reg, uint64_t &value)
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{
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DWORD size = 0;
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if (!DeviceIoControl(driver, IOCTL_READ_MSR, ®, sizeof(reg), &value, sizeof(value), &size, nullptr)) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "cannot read MSR 0x%08" PRIx32, tag, reg);
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return false;
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}
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return true;
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return DeviceIoControl(driver, IOCTL_READ_MSR, ®, sizeof(reg), &value, sizeof(value), &size, nullptr) != 0;
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}
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@ -225,6 +219,8 @@ static MsrItem rdmsr(HANDLE driver, uint32_t reg)
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{
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uint64_t value = 0;
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if (!rdmsr(driver, reg, value)) {
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LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "cannot read MSR 0x%08" PRIx32, tag, reg);
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return {};
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}
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