From 748365d6e37c3d3b6728a2dd9caf8dc30d2e8905 Mon Sep 17 00:00:00 2001
From: SChernykh <15806605+SChernykh@users.noreply.github.com>
Date: Sat, 3 Aug 2024 11:01:18 +0200
Subject: [PATCH] Added Zen5 detection

Preliminary Zen5 support, MSR mod is not ready yet.
---
 src/backend/cpu/interfaces/ICpuInfo.h     | 6 ++++--
 src/backend/cpu/platform/BasicCpuInfo.cpp | 7 ++++++-
 src/crypto/randomx/jit_compiler_x86.cpp   | 4 ++++
 src/crypto/rx/RxConfig.cpp                | 6 +++++-
 4 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/backend/cpu/interfaces/ICpuInfo.h b/src/backend/cpu/interfaces/ICpuInfo.h
index e9d795cec..8d10d4d29 100644
--- a/src/backend/cpu/interfaces/ICpuInfo.h
+++ b/src/backend/cpu/interfaces/ICpuInfo.h
@@ -52,7 +52,8 @@ public:
         ARCH_ZEN_PLUS,
         ARCH_ZEN2,
         ARCH_ZEN3,
-        ARCH_ZEN4
+        ARCH_ZEN4,
+        ARCH_ZEN5
     };
 
     enum MsrMod : uint32_t {
@@ -60,12 +61,13 @@ public:
         MSR_MOD_RYZEN_17H,
         MSR_MOD_RYZEN_19H,
         MSR_MOD_RYZEN_19H_ZEN4,
+        MSR_MOD_RYZEN_1AH_ZEN5,
         MSR_MOD_INTEL,
         MSR_MOD_CUSTOM,
         MSR_MOD_MAX
     };
 
-#   define MSR_NAMES_LIST "none", "ryzen_17h", "ryzen_19h", "ryzen_19h_zen4", "intel", "custom"
+#   define MSR_NAMES_LIST "none", "ryzen_17h", "ryzen_19h", "ryzen_19h_zen4", "ryzen_1Ah_zen5", "intel", "custom"
 
     enum Flag : uint32_t {
         FLAG_AES,
diff --git a/src/backend/cpu/platform/BasicCpuInfo.cpp b/src/backend/cpu/platform/BasicCpuInfo.cpp
index 3ddce3e7e..30a78f828 100644
--- a/src/backend/cpu/platform/BasicCpuInfo.cpp
+++ b/src/backend/cpu/platform/BasicCpuInfo.cpp
@@ -64,7 +64,7 @@ static_assert(kCpuFlagsSize == ICpuInfo::FLAG_MAX, "kCpuFlagsSize and FLAG_MAX m
 
 
 #ifdef XMRIG_FEATURE_MSR
-constexpr size_t kMsrArraySize                                  = 6;
+constexpr size_t kMsrArraySize                                  = 7;
 static const std::array<const char *, kMsrArraySize> msrNames   = { MSR_NAMES_LIST };
 static_assert(kMsrArraySize == ICpuInfo::MSR_MOD_MAX, "kMsrArraySize and MSR_MOD_MAX mismatch");
 #endif
@@ -260,6 +260,11 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
                     }
                     break;
 
+                case 0x1a:
+                    m_arch = ARCH_ZEN5;
+                    m_msrMod = MSR_MOD_RYZEN_1AH_ZEN5;
+                    break;
+
                 default:
                     m_msrMod = MSR_MOD_NONE;
                     break;
diff --git a/src/crypto/randomx/jit_compiler_x86.cpp b/src/crypto/randomx/jit_compiler_x86.cpp
index 7f9fb3b68..f66c4cbed 100644
--- a/src/crypto/randomx/jit_compiler_x86.cpp
+++ b/src/crypto/randomx/jit_compiler_x86.cpp
@@ -266,6 +266,10 @@ namespace randomx {
 						// AVX2 init is slower on Zen4
 						initDatasetAVX2 = false;
 						break;
+					case xmrig::ICpuInfo::ARCH_ZEN5:
+						// TODO: test it
+						initDatasetAVX2 = false;
+						break;
 					}
 				}
 			}
diff --git a/src/crypto/rx/RxConfig.cpp b/src/crypto/rx/RxConfig.cpp
index cd1969354..4931e64d5 100644
--- a/src/crypto/rx/RxConfig.cpp
+++ b/src/crypto/rx/RxConfig.cpp
@@ -53,13 +53,17 @@ static const std::array<const char *, RxConfig::ModeMax> modeNames = { "auto", "
 
 
 #ifdef XMRIG_FEATURE_MSR
-constexpr size_t kMsrArraySize = 6;
+constexpr size_t kMsrArraySize = 7;
 
 static const std::array<MsrItems, kMsrArraySize> msrPresets = {
     MsrItems(),
     MsrItems{{ 0xC0011020, 0ULL }, { 0xC0011021, 0x40ULL, ~0x20ULL }, { 0xC0011022, 0x1510000ULL }, { 0xC001102b, 0x2000cc16ULL }},
     MsrItems{{ 0xC0011020, 0x0004480000000000ULL }, { 0xC0011021, 0x001c000200000040ULL, ~0x20ULL }, { 0xC0011022, 0xc000000401570000ULL }, { 0xC001102b, 0x2000cc10ULL }},
     MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
+
+    // TODO: Tune it for Zen5 when it's available
+    MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
+
     MsrItems{{ 0x1a4, 0xf }},
     MsrItems()
 };