mirror of
https://github.com/xmrig/xmrig.git
synced 2024-12-23 12:09:22 +00:00
Update libcpuid to recent git version.
This commit is contained in:
parent
cf76d9254a
commit
1f609c7ebd
8 changed files with 991 additions and 929 deletions
21
src/3rdparty/libcpuid/asm-bits.c
vendored
21
src/3rdparty/libcpuid/asm-bits.c
vendored
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@ -32,7 +32,7 @@ int cpuid_exists_by_eflags(void)
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#if defined(PLATFORM_X64)
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return 1; /* CPUID is always present on the x86_64 */
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#elif defined(PLATFORM_X86)
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# if defined(COMPILER_GCC)
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# if defined(COMPILER_GCC) || defined(COMPILER_CLANG)
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int result;
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__asm __volatile(
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" pushfl\n"
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@ -70,6 +70,8 @@ int cpuid_exists_by_eflags(void)
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# else
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return 0;
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# endif /* COMPILER_MICROSOFT */
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#elif defined(PLATFORM_ARM)
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return 0;
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#else
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return 0;
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#endif /* PLATFORM_X86 */
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@ -82,7 +84,7 @@ int cpuid_exists_by_eflags(void)
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*/
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void exec_cpuid(uint32_t *regs)
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{
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#ifdef COMPILER_GCC
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# if defined(COMPILER_GCC) || defined(COMPILER_CLANG)
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# ifdef PLATFORM_X64
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__asm __volatile(
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" mov %0, %%rdi\n"
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@ -109,7 +111,7 @@ void exec_cpuid(uint32_t *regs)
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:"m"(regs)
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:"memory", "eax", "rdi"
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);
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# else
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# elif defined(PLATFORM_X86)
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__asm __volatile(
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" mov %0, %%edi\n"
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@ -135,6 +137,7 @@ void exec_cpuid(uint32_t *regs)
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:"m"(regs)
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:"memory", "eax", "edi"
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);
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# elif defined(PLATFORM_ARM)
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# endif /* COMPILER_GCC */
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#else
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# ifdef COMPILER_MICROSOFT
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@ -173,13 +176,18 @@ void exec_cpuid(uint32_t *regs)
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void cpu_rdtsc(uint64_t* result)
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{
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uint32_t low_part, hi_part;
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#ifdef COMPILER_GCC
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#if defined(COMPILER_GCC) || defined(COMPILER_CLANG)
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#ifdef PLATFORM_ARM
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low_part = 0;
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hi_part = 0;
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#else
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__asm __volatile (
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" rdtsc\n"
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" mov %%eax, %0\n"
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" mov %%edx, %1\n"
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:"=m"(low_part), "=m"(hi_part)::"memory", "eax", "edx"
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);
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#endif
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#else
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# ifdef COMPILER_MICROSOFT
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__asm {
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@ -198,12 +206,14 @@ void cpu_rdtsc(uint64_t* result)
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#ifdef INLINE_ASM_SUPPORTED
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void busy_sse_loop(int cycles)
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{
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#ifdef COMPILER_GCC
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# if defined(COMPILER_GCC) || defined(COMPILER_CLANG)
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#ifndef __APPLE__
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# define XALIGN ".balign 16\n"
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#else
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# define XALIGN ".align 4\n"
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#endif
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#ifdef PLATFORM_ARM
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#else
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__asm __volatile (
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" xorps %%xmm0, %%xmm0\n"
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" xorps %%xmm1, %%xmm1\n"
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@ -510,6 +520,7 @@ void busy_sse_loop(int cycles)
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" jnz 1b\n"
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::"a"(cycles)
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);
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#endif
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#else
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# ifdef COMPILER_MICROSOFT
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__asm {
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20
src/3rdparty/libcpuid/asm-bits.h
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20
src/3rdparty/libcpuid/asm-bits.h
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@ -29,20 +29,38 @@
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/* Determine Compiler: */
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#if defined(_MSC_VER)
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#if !defined(COMPILER_MICROSOFT)
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# define COMPILER_MICROSOFT
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#endif
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#elif defined(__GNUC__)
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#if !defined(COMPILER_GCC)
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# define COMPILER_GCC
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#endif
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#elif defined(__clang__)
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#if !defined(COMPILER_CLANG)
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# define COMPILER_CLANG
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#endif
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#endif
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/* Determine Platform */
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#if defined(__x86_64__) || defined(_M_AMD64)
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#if !defined(PLATFORM_X64)
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# define PLATFORM_X64
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#endif
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#elif defined(__i386__) || defined(_M_IX86)
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#if !defined(PLATFORM_X86)
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# define PLATFORM_X86
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#endif
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#elif defined(__ARMEL__)
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#if !defined(PLATFORM_ARM)
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# define PLATFORM_ARM
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#endif
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#endif
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/* Under Windows/AMD64 with MSVC, inline assembly isn't supported */
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#if (defined(COMPILER_GCC) && defined(PLATFORM_X64)) || defined(PLATFORM_X86)
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#if (((defined(COMPILER_GCC) || defined(COMPILER_CLANG))) && \
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(defined(PLATFORM_X64) || defined(PLATFORM_X86) || defined(PLATFORM_ARM))) || \
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(defined(COMPILER_MICROSOFT) && defined(PLATFORM_X86))
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# define INLINE_ASM_SUPPORTED
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#endif
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56
src/3rdparty/libcpuid/cpuid_main.c
vendored
56
src/3rdparty/libcpuid/cpuid_main.c
vendored
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@ -221,42 +221,42 @@ static void load_features_common(struct cpu_raw_data_t* raw, struct cpu_id_t* da
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static cpu_vendor_t cpuid_vendor_identify(const uint32_t *raw_vendor, char *vendor_str)
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{
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int i;
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cpu_vendor_t vendor = VENDOR_UNKNOWN;
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const struct { cpu_vendor_t vendor; char match[16]; }
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matchtable[NUM_CPU_VENDORS] = {
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/* source: http://www.sandpile.org/ia32/cpuid.htm */
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{ VENDOR_INTEL , "GenuineIntel" },
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{ VENDOR_AMD , "AuthenticAMD" },
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{ VENDOR_CYRIX , "CyrixInstead" },
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{ VENDOR_NEXGEN , "NexGenDriven" },
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{ VENDOR_TRANSMETA , "GenuineTMx86" },
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{ VENDOR_UMC , "UMC UMC UMC " },
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{ VENDOR_CENTAUR , "CentaurHauls" },
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{ VENDOR_RISE , "RiseRiseRise" },
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{ VENDOR_SIS , "SiS SiS SiS " },
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{ VENDOR_NSC , "Geode by NSC" },
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};
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int i;
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cpu_vendor_t vendor = VENDOR_UNKNOWN;
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const struct { cpu_vendor_t vendor; char match[16]; }
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matchtable[NUM_CPU_VENDORS] = {
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/* source: http://www.sandpile.org/ia32/cpuid.htm */
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{ VENDOR_INTEL , "GenuineIntel" },
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{ VENDOR_AMD , "AuthenticAMD" },
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{ VENDOR_CYRIX , "CyrixInstead" },
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{ VENDOR_NEXGEN , "NexGenDriven" },
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{ VENDOR_TRANSMETA , "GenuineTMx86" },
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{ VENDOR_UMC , "UMC UMC UMC " },
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{ VENDOR_CENTAUR , "CentaurHauls" },
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{ VENDOR_RISE , "RiseRiseRise" },
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{ VENDOR_SIS , "SiS SiS SiS " },
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{ VENDOR_NSC , "Geode by NSC" },
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};
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memcpy(vendor_str + 0, &raw_vendor[1], 4);
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memcpy(vendor_str + 4, &raw_vendor[3], 4);
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memcpy(vendor_str + 8, &raw_vendor[2], 4);
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vendor_str[12] = 0;
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memcpy(vendor_str + 0, &raw_vendor[1], 4);
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memcpy(vendor_str + 4, &raw_vendor[3], 4);
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memcpy(vendor_str + 8, &raw_vendor[2], 4);
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vendor_str[12] = 0;
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/* Determine vendor: */
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for (i = 0; i < NUM_CPU_VENDORS; i++)
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if (!strcmp(vendor_str, matchtable[i].match)) {
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vendor = matchtable[i].vendor;
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break;
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}
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return vendor;
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/* Determine vendor: */
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for (i = 0; i < NUM_CPU_VENDORS; i++)
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if (!strcmp(vendor_str, matchtable[i].match)) {
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vendor = matchtable[i].vendor;
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break;
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}
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return vendor;
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}
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static int cpuid_basic_identify(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
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{
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int i, j, basic, xmodel, xfamily, ext;
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char brandstr[64] = {0};
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data->vendor = cpuid_vendor_identify(raw->basic_cpuid[0], data->vendor_str);
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data->vendor = cpuid_vendor_identify(raw->basic_cpuid[0], data->vendor_str);
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if (data->vendor == VENDOR_UNKNOWN)
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return set_error(ERR_CPU_UNKN);
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37
src/3rdparty/libcpuid/libcpuid.h
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37
src/3rdparty/libcpuid/libcpuid.h
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@ -82,6 +82,7 @@
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*/
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/** @defgroup libcpuid LibCPUID
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* @brief LibCPUID provides CPU identification
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@{ */
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/* Include some integer type specifications: */
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@ -535,23 +536,23 @@ typedef enum {
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* @brief Describes common library error codes
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*/
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typedef enum {
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ERR_OK = 0, /*!< "No error" */
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ERR_NO_CPUID = -1, /*!< "CPUID instruction is not supported" */
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ERR_NO_RDTSC = -2, /*!< "RDTSC instruction is not supported" */
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ERR_NO_MEM = -3, /*!< "Memory allocation failed" */
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ERR_OPEN = -4, /*!< "File open operation failed" */
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ERR_BADFMT = -5, /*!< "Bad file format" */
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ERR_NOT_IMP = -6, /*!< "Not implemented" */
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ERR_CPU_UNKN = -7, /*!< "Unsupported processor" */
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ERR_NO_RDMSR = -8, /*!< "RDMSR instruction is not supported" */
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ERR_NO_DRIVER= -9, /*!< "RDMSR driver error (generic)" */
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ERR_NO_PERMS = -10, /*!< "No permissions to install RDMSR driver" */
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ERR_EXTRACT = -11, /*!< "Cannot extract RDMSR driver (read only media?)" */
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ERR_HANDLE = -12, /*!< "Bad handle" */
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ERR_INVMSR = -13, /*!< "Invalid MSR" */
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ERR_INVCNB = -14, /*!< "Invalid core number" */
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ERR_HANDLE_R = -15, /*!< "Error on handle read" */
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ERR_INVRANGE = -16, /*!< "Invalid given range" */
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ERR_OK = 0, /*!< No error */
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ERR_NO_CPUID = -1, /*!< CPUID instruction is not supported */
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ERR_NO_RDTSC = -2, /*!< RDTSC instruction is not supported */
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ERR_NO_MEM = -3, /*!< Memory allocation failed */
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ERR_OPEN = -4, /*!< File open operation failed */
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ERR_BADFMT = -5, /*!< Bad file format */
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ERR_NOT_IMP = -6, /*!< Not implemented */
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ERR_CPU_UNKN = -7, /*!< Unsupported processor */
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ERR_NO_RDMSR = -8, /*!< RDMSR instruction is not supported */
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ERR_NO_DRIVER= -9, /*!< RDMSR driver error (generic) */
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ERR_NO_PERMS = -10, /*!< No permissions to install RDMSR driver */
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ERR_EXTRACT = -11, /*!< Cannot extract RDMSR driver (read only media?) */
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ERR_HANDLE = -12, /*!< Bad handle */
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ERR_INVMSR = -13, /*!< Invalid MSR */
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ERR_INVCNB = -14, /*!< Invalid core number */
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ERR_HANDLE_R = -15, /*!< Error on handle read */
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ERR_INVRANGE = -16, /*!< Invalid given range */
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} cpu_error_t;
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/**
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@ -668,7 +669,7 @@ struct cpu_epc_t cpuid_get_epc(int index, const struct cpu_raw_data_t* raw);
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const char* cpuid_lib_version(void);
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#ifdef __cplusplus
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}; /* extern "C" */
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} /* extern "C" */
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#endif
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5
src/3rdparty/libcpuid/libcpuid_internal.h
vendored
5
src/3rdparty/libcpuid/libcpuid_internal.h
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@ -75,8 +75,9 @@ enum _intel_bits_t {
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_3 = LBIT( 14 ),
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_5 = LBIT( 15 ),
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_7 = LBIT( 16 ),
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XEON_ = LBIT( 17 ),
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ATOM_ = LBIT( 18 ),
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_9 = LBIT( 17 ),
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XEON_ = LBIT( 18 ),
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ATOM_ = LBIT( 19 ),
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};
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typedef enum _intel_bits_t intel_bits_t;
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28
src/3rdparty/libcpuid/libcpuid_types.h
vendored
28
src/3rdparty/libcpuid/libcpuid_types.h
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@ -32,6 +32,32 @@
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#ifndef __LIBCPUID_TYPES_H__
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#define __LIBCPUID_TYPES_H__
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#include <stdint.h>
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#if !defined(_MSC_VER) || _MSC_VER >= 1600
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# include <stdint.h>
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#else
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/* we have to provide our own: */
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# if !defined(__int32_t_defined)
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typedef int int32_t;
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# endif
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# if !defined(__uint32_t_defined)
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typedef unsigned uint32_t;
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# endif
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typedef signed char int8_t;
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typedef unsigned char uint8_t;
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typedef signed short int16_t;
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typedef unsigned short uint16_t;
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#if (defined _MSC_VER) && (_MSC_VER <= 1300)
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/* MSVC 6.0: no long longs ... */
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typedef signed __int64 int64_t;
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typedef unsigned __int64 uint64_t;
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#else
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/* all other sane compilers: */
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typedef signed long long int64_t;
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typedef unsigned long long uint64_t;
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#endif
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#endif
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#endif /* __LIBCPUID_TYPES_H__ */
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4
src/3rdparty/libcpuid/recog_amd.c
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4
src/3rdparty/libcpuid/recog_amd.c
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@ -49,6 +49,10 @@ enum _amd_model_codes_t {
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_1400,
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_1500,
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_1600,
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_1900,
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_2400,
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_2500,
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_2700,
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};
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static void load_amd_features(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
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3
src/3rdparty/libcpuid/recog_intel.c
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3
src/3rdparty/libcpuid/recog_intel.c
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@ -376,7 +376,7 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
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bits |= bit_matchtable[i].bit;
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}
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if ((i = match_pattern(bs, "Core(TM) [im][357]")) != 0) {
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if ((i = match_pattern(bs, "Core(TM) [im][3579]")) != 0) {
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bits |= CORE_;
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i--;
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switch (bs[i + 9]) {
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@ -387,6 +387,7 @@ static intel_code_and_bits_t get_brand_code_and_bits(struct cpu_id_t* data)
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case '3': bits |= _3; break;
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case '5': bits |= _5; break;
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case '7': bits |= _7; break;
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case '9': bits |= _9; break;
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}
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}
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for (i = 0; i < COUNT_OF(matchtable); i++)
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