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Document critical race condition due to two distinct clocks operating over the same data

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Luke Parker 2023-11-09 08:41:22 -05:00
parent e8e9e212df
commit bf41009c5a
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2 changed files with 5 additions and 3 deletions
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4
processor/src/multisigs/mod.rs
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@ -869,6 +869,10 @@ impl<D: Db, N: Network> MultisigManager<D, N> {
continue;
}
// TODO: Both save_forwarded_output and take_forwarded_output have to happen on the
// same clock. Right now, one occurs on Substrate block ack, one occurs on scan.
// TODO: To resolve this, this function has to create the plans for
// forwarding/refunding outputs.
if let Some(instruction) =
MultisigsDb::<N, D>::take_forwarded_output(txn, output.balance())
{

4
processor/src/multisigs/scanner.rs
View file

@ -677,9 +677,7 @@ impl<N: Network, D: Db> Scanner<N, D> {
// - This is an activation block
// - This is a retirement block
// - There's outputs
// as only those are blocks are meaningful and warrant obtaining synchrony over
// TODO: Consider not obtaining synchrony over the retirement block depending on how the
// hand-off is implemented on the Substrate side of things
// as only those blocks are meaningful and warrant obtaining synchrony over
let is_retirement_block =
ScannerDb::<N, D>::retirement_block(&db, &scanner.keys[0].1) == Some(block_being_scanned);
let sent_block = if has_activation || is_retirement_block || (!outputs.is_empty()) {